The present invention relates generally to semiconductor device manufacturing and, more particularly, to methods of protecting exposed metal gate structures from etching processes during integrated circuit manufacturing.
In standard complementary metal oxide semiconductor (CMOS) devices, polysilicon is typically used as the gate material. The technology of fabricating CMOS devices using polysilicon gates has been in a constant state of development, and is now widely used in the semiconductor industry. One advantage of using polysilicon gates is that they can sustain high temperatures. However, there are also some problems associated with using a polysilicon gate. For example, due to the poly-depletion effect, polysilicon gates commonly used in CMOS devices are becoming a gating factor in chip performance for channel lengths of 0.1 micron and below. Another problem with polysilicon gates is that the dopant material in the polysilicon gate (e.g., boron) can easily diffuse through the thin gate dielectric, causing further degradation of the device performance.
Thus, one proposed way of improving the performance of sub-micron transistors is to use metal gate stacks (e.g., polysilicon over metal) in place of conventional polysilicon gates, particularly with the advent of high dielectric constant (high-k) gate dielectric materials such as, for example, hafnium dioxide (HfO2), hafnium silicon oxynitride (HfSiON), and zirconium dioxide (ZrO2). The metal gate electrode portions of the gate stack are configured with an appropriate work function, and may include materials such as, for example, lanthanum (La), aluminum (Al), magnesium (Mg), ruthenium (Ru), titanium-based materials such as titanium (Ti) and titanium nitride (TiN), tantalum-based materials such as tantalum (Ta) and tantalum nitride (TaN) or tantalum carbide (TaC).
During the fabrication of an integrated circuit device, structures such field effect transistor (FET) gate stacks are exposed to various etchant and cleaning chemistries. To protect the gate stack, particularly a gate stack comprising sensitive materials such as high-k dielectrics and metal gate-forming materials, a silicon nitride spacer is formed adjacent sidewalls of the gate stack. However, depending on non-uniformities of the gate stack fabrication process or non-uniformities created during preparation of the semiconductor substrate prior to fabrication of the gate stacks, a silicon nitride spacer may not be adequate to protect the high-k metal gate (HKMG) stack.
For example, prior to fabrication of the gate stacks, shallow trench isolation (STI) regions are formed within a semiconductor substrate to electrically isolate other regions of the semiconductor substrate. Typically, the STI regions are fabricated by etching regions of the substrate (exposed by a patterned hardmask over the substrate) to form trenches therein, and depositing an insulating material such as silicon oxide in the trenches. The deposited oxide is then planarized, followed by removal of the hardmask used in creating the STI pattern. In order to remove the hardmask, a wet etch chemistry is applied, which can result in the slight lateral etching of the STI oxide material. This lateral etching in turn causes a divot or void to be formed at the edge of the STI region bordering the active semiconductor region.
Where a gate stack layer is formed at the border of the active and STI regions (i.e., over a divot or step height in topography), portions of the metal gate material may be left unprotected by sidewall spacers and thus susceptible to wet etch chemistries during subsequent middle-of-line (MOL) processing operations. Such etching can create a void within the gate stack and thus device failure and gate lift-off. In addition to STI divots, metal gate footings can also result in gate structures formed on a planar surface, such as dummy gates formed on STI regions that are adjacent an active area where a step height is present. Footings can also result from various non-uniformities in reactive ion etching processes, photolithography processes used to form the gate stacks, and the like.